| 摘要: |
| GIDC C密码算法芯片适用于计算机网络安全领域 ,该芯片采用超大规模集成电路工艺 ,是集CPU、加解密运算部件、存储器等为一体的SOC芯片。采用了自顶向下的设计方法 ,重点讨论了芯片的总体实现方案及CPU ,RSA ,DES等模块的内部结构 ,分析了功耗、可靠性、仿真等设计难点及解决办法。仿真和物理验证的结果表明 ,所设计的电路工作正常 ,运行稳定可靠。 10 2 4bit的RSA加 /解密速率为 5次·s-1,DES加 /解密速率达 2Mbit·s-1,达到了设计的要求。 |
| 关键词: GIDC-C密码算法 芯片研制 产品开发 计算机网络 集成电路工艺 解密运算部件 存储器 |
| DOI：10.11841/j.issn.1007-4333.2003.04.101 |
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| 基金项目:国家 8 6 3计划项目 (2 0 0 1AA14 10 30 )资助 |
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| Design of chip based on cryptogrammic arithmetic |
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| Abstract: |
| GIDC-C was designed for computer network. Fabricated with very large scale integration technology, the chip is a soc which include CPU,RSA,DES module. The top-down design methodology was adopted. The ASIC scheme and detailed structure of CPU,RSA,DES were presented. Power consumption, reliability and simulation is analyzed. The result of simulation and verification validates that the circuit works stably and reliably. The Encryption rate was reached to 5 times per second for RSA and 2?Mbit per second for DES. |
| Key words: CPU,SOC,encryption, |
